The present invention is described for testing IC (integrated circuit) packages during manufacture of IC packages. However, the present invention may be applied for testing any articles of manufacture.
FIG. 1 show a flowchart of steps for testing IC packages within a tester that assigns each tested IC package to a respective one of a plurality of distribution bins. One example of such a tester is available from Advantest Corp. headquartered in Tokyo, Japan with a regional headquarter in Santa Clara, Calif. Each distribution bin is associated with a test result condition.
For example, a tested IC package may be assigned to distribution bin #1 when the IC package passes testing with a first operating current, to distribution bin #2 when the IC package passes testing with a second operating current, and so on to distribution bin #5 when the IC package passes testing with a fifth operating current. Or, the IC package may be assigned to distribution bin #6 when the IC package fails testing because a short circuit is detected, to distribution bin #7 when the IC package fails testing because an open circuit is detected, to distribution bin #8 when the IC package fails testing because a level of current flowing through the IC package is greater than an acceptable level, and so on.
Referring to FIG. 1, an insertion unit of IC packages is tested at a time by the tester (step 102 of FIG. 1). For example, the insertion unit of the tester may have thirty-two sockets for holding and testing thirty-two IC packages at a time. After testing of the thirty-two IC packages, the tester generates distribution bin data including assignment of a respective one of the plurality of bins for each of the tested IC packages (step 104 of FIG. 1).
IC packages are typically manufactured in a lot with a lot size of thousands of IC packages such as 7,000 IC packages for example. If the whole lot of IC packages has not yet been tested (step 106 of FIG. 1), then the tester tests a next insertion unit of IC packages to repeat steps 102 and 104 with the next insertion unit of IC packages. Steps 102, 104, and 106 are repeated for each insertion unit of IC packages at a rate of three times per minute until the whole lot of IC packages has been tested.
When the whole lot of IC packages has been tested (step 108 of FIG. 1), summary test data is generated (step 108 of FIG. 1) for the whole lot of IC packages. Such summary test data includes a yield percentage of IC packages for each distribution bin and a total yield percentage of IC packages passing the test.
In the prior art, the whole lot of IC packages are first tested according to the flowchart of FIG. 1. Then, a production engineer reviews the summary test data to determine whether the yield percentages are acceptable. If such yield percentages are not acceptable, the production engineer attempts to correct for any conditions leading to test failure, and the failed IC packages are retested in a rescreen process. For example, the production engineer may check and correct for conditions of socket failure, device mixing, and incorrect die or accessory attachment to the tester.
Thus, in the prior art, the production engineer who analyzes the summary test data is required to be highly skilled and may still make an error in human judgment in deciding disposition of the lot of tested IC packages. Furthermore, during IC package manufacture, many different types of IC packages for diverse IC products are tested. The production engineer is required to keep track of different criteria for analyzing the summary test data for numerous different types of IC products.
Furthermore, in the prior art, the summary test data is analyzed after the whole lot of IC packages are tested. Such testing of the whole lot may require a relatively long period of time such as even 10–20 hours for example. In addition, as IC products are becoming more complicated in structure and operation, the time period required for testing the whole lot of IC packages is ever increasing. If a substantial majority of the lot of IC packages fails testing, a large number of such failed IC packages are retested again.
A rescreen condition occurs during testing and results in a substantial majority of the IC packages failing but not because of the IC package being faulty. Examples of rescreen conditions include device mixing (where unintended IC packages are tested), insertion failure (where the IC packages are inserted into the sockets of the tester with wrong orientation), socket failure (where a socket within the tester is faulty), wrong die or fixture installation (where a wrong part that does not correspond to the tested IC package is installed onto the tester), and a bug in the tester program (where an improper level of test current is sourced into the IC package by the tester).
In the prior art, occurrence of a rescreen condition is not determined until the whole lot of IC packages has been tested. As a result, in the prior art, substantial time and tester utilization is wasted for first testing the whole lot of IC packages and second for retesting a substantial majority of the IC packages after occurrence of the rescreen condition.
Thus, a mechanism is desired for automatically determining occurrence of a rescreen condition more immediately in real-time long before the whole lot of IC packages is tested. Such a mechanism maximizes tester utilization in testing for actual operation of the IC packages.